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ECE/EDS Seminar: Celerity: An Open-Source RISC-V Tiered Accelerator Fabric

Friday, Sep 15, 2017 at 12:00 PM [.ics]
233 Phillips Hall

Abstract
The recent trend towards accelerator-centric architectures, especially in the context of deep learning, has renewed the need for demonstrating new research ideas in prototype systems with custom chips. Unfortunately, building such research prototypes is tremendously challenging. This talk describes the Celerity system-on-chip (SoC), a 5×5 mm 350M-transistor chip in TSMC 16 nm that was developed as part of the DARPA CRAFT program intended to develop new methodologies for rapid chip development. On the one hand, the Celerity SoC explores and evaluates binarized neural networks that are implemented across a tiered parallel architecture including a general-purpose tier, a massively parallel tier, and a specialized accelerator tier. On the other hand, the Celerity SoC demonstrates the possibility of taping out a complex SoC (1) in only nine months, (2) with a team of junior graduate students, (3) spread across four locations, (4) in a 16nm advanced process, (5) with a budget of $1.2M. The talk will be delivered by three graduate students and will cover various highlights of the Celerity SoC.

 
Bios

Khalid Al-Hawaj is a third year ECE PhD student working with Professor Christopher Batten. He earned his BSc in Computer Engineering from KFUPM and M.Eng. from Harvard University. He is interested in conducting vertically integrated computer architecture research with focus on hardware/software co-design.

Ritchie Zhao is a fourth year ECE PhD student at Cornell University under Professor Zhiru Zhang. He received his B.S. from the University of Toronto in 2014. His research interests include hardware specialization for deep learning on FPGAs, as well as high-level synthesis for productive hardware design.

Christopher Torng is a sixth year ECE PhD student working with Professor Christopher Batten. He is interested in heterogeneous systems based on hardware accelerators and how to connect such systems up the stack (e.g., with work-stealing runtimes) as well as down the stack (e.g., recent circuits work on integrated voltage regulation). He has also helped to build research prototype systems ranging from older 130nm down to more advanced 16nm designs.

 

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